Phase frequency detection device

ABSTRACT

Filter circuitry is constituted by transversal filters which are connected in parallel to each other. The transversal filters change amplitude and a phase of an input digital signal X in [n·T s ] and output different digital signals X 1 [n·T s ], X 2 [n·T s ], and X 3 [n·T s ] as respective resulting digital signals whose amplitude and phase have been changed. A phase frequency computer computes a phase θ X [n·T s ] and a frequency f X [n·T s ] of the input digital signal X in [n·T s ] by performing phase computation and frequency computation using the digital signals X 1 [n·T s ], X 2 [n·T s ], and X 3 [n·T s ] output by the transversal filters.

TECHNICAL FIELD

The invention relates to a phase frequency detection device that ismounted on, for example, a signal measuring device, etc., and thatdetects a phase and a frequency of an input digital signal.

BACKGROUND ART

A phase frequency detection device disclosed in Patent Literature 1mentioned later is constituted by A/D conversion circuitry, a digitalBPF, delay compensation circuitry, Hilbert transformation circuitry,phase angle computation circuitry, a memory, and frequency computationcircuitry.

The A/D conversion circuitry converts an input analog signal into adigital signal and outputs the digital signal to the digital BPF.

The digital BPF outputs only a digital signal in a desired frequencyband among digital signals output by the A/D conversion circuitry to thedelay compensation circuitry and the Hilbert transformation circuitry.

After receiving the digital signal of the desired frequency band fromthe digital BPF, the delay compensation circuitry performs a time-shiftof the digital signal by a time corresponding to a delay time caused bya Hilbert transformation in the Hilbert transformation circuitry.

After receiving the digital signal of the desired frequency band fromthe digital BPF, the Hilbert transformation circuitry performs a Hilberttransformation on the digital signal, and thereby outputs a signaldiffering from the digital signal in a phase by 90 degrees.

Note that the higher the accuracy required for the amplitude and phaseof an output signal from the Hilbert transformation circuitry, thelonger the delay time resulting from a Hilbert transformation.Therefore, the number of stages of delay circuitry included in the delaycompensation circuitry increases, resulting in several tens to hundredsof stages.

The phase angle computation circuitry computes a phase of the inputanalog signal by performing an arctangent computation based on theoutput signal of the delay compensation circuitry and the output signalof the Hilbert transformation circuitry, and outputs the resulting phaseto the memory and the frequency computation circuitry.

The frequency computation circuitry computes a frequency of the inputanalog signal by using the phase output by the phase angle computationcircuitry and a phase obtained at one sampling time before, which hasbeen stored in the memory.

CITATION LIST

Patent Literature 1: JP 2005-91255 A (e.g., paragraph [0008] and FIG. 1)

SUMMARY OF INVENTION

Since the conventional phase frequency detection device is constitutedin the above-described manner, the higher the accuracy required for theamplitude and phase of an output signal from the Hilbert transformationcircuitry, the longer the delay time resulting from a Hilberttransformation, resulting in increase in the number of stages of delaycircuitry of the delay compensation circuitry. Hence, in a case where asignal to be input is a short-pulse signal, there may cause a problemthat the phase and the frequency of the input signal are hard to bedetected. In addition, there may be another problem that, as the numberof stages of delay circuitry increases, the circuitry size increases andalso the power consumption resulting from digital computation increases.

The invention is made to solve problems described above. An object ofthe invention is to obtain a phase frequency detection device that iscapable of detecting a phase and a frequency even if a signal to beinput is a short-pulse signal, and also capable of suppressing increasein circuitry size and increase in power consumption caused by increasein the number of stages of delay circuitry.

A phase frequency detection device according to the invention includes:filter circuitry including a plurality of transversal filters which areconnected in parallel to each other, the plurality of transversalfilters changing amplitude and a phase of an input digital signal andoutputting different digital signals as respective resulting digitalsignals whose amplitude and phase have been changed; and a phasefrequency computer to compute a phase and a frequency of the inputdigital signal by performing phase computation and frequency computationusing the digital signals output by the plurality of transversalfilters.

According to the invention, it is constituted such that filter circuitryincluding a plurality of transversal filters which are connected inparallel to each other, the plurality of transversal filters changingamplitude and a phase of an input digital signal and outputtingdifferent digital signals as respective resulting digital signals whoseamplitude and phase have been changed; and a phase frequency computer tocompute a phase and a frequency of the input digital signal byperforming phase computation and frequency computation using the digitalsignals output by the plurality of transversal filters. Thus, there areadvantageous effects that, even if a digital signal to be input is ashort-pulse signal, a phase and a frequency thereof can be detected, andincrease in circuitry size and increase in power consumption caused byincrease in the number of stages of delay circuitry can be suppressed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a configuration diagram illustrating a phase frequencydetection device of Embodiment 1 of the invention.

FIG. 2 is a configuration diagram illustrating subtraction-typefirst-order transversal filters and addition-type first-ordertransversal filters.

FIG. 3 is a configuration diagram illustrating a phase frequencydetection device of Embodiment 2 of the invention.

FIG. 4 is a configuration diagram illustrating a phase frequencydetection device of Embodiment 3 of the invention.

FIG. 5 is a configuration diagram illustrating filter circuitry 1 of aphase frequency detection device of Embodiment 4 of the invention.

FIG. 6 is a configuration diagram illustrating filter circuitry 1 of aphase frequency detection device of Embodiment 5 of the invention.

FIG. 7 is a configuration diagram illustrating filter circuitry 1 of aphase frequency detection device of Embodiment 6 of the invention.

FIG. 8 is a configuration diagram illustrating a transversal filter 10of a phase frequency detection device of Embodiment 7 of the invention.

FIG. 9 is a configuration diagram illustrating a transversal filter 20of a phase frequency detection device of Embodiment 8 of the invention.

FIG. 10 is a configuration diagram illustrating a transversal filter 30of a phase frequency detection device of Embodiment 9 of the invention.

FIG. 11 is a configuration diagram illustrating filter circuitry 1 of aphase frequency detection device of Embodiment 10 of the invention.

FIG. 12 is a configuration diagram illustrating filter circuitry 1 of aphase frequency detection device of the Embodiment 10 of the invention.

FIG. 13 is a configuration diagram illustrating filter circuitry 1 of aphase frequency detection device of the Embodiment 10 of the invention.

FIG. 14 is a configuration diagram illustrating a phase frequencydetection device of Embodiment 11 of the invention.

FIG. 15 is a configuration diagram illustrating a phase frequencydetection device of the Embodiment 11 of the invention.

DESCRIPTION OF EMBODIMENTS

In order to describe the invention in more detail, modes for carryingout the invention will be described below with reference to theaccompanying drawings.

Embodiment 1

FIG. 1 is a configuration diagram illustrating a phase frequencydetection device of Embodiment 1 of the invention.

In FIG. 1, filter circuitry 1 includes transversal filters 10, 20, and30, which are connected in parallel to each other. The transversalfilters 10, 20, and 30 changes amplitude and a phase of an input digitalsignal X_(in) and output different digital signals X₁, X₂, and X₃ asrespective resulting digital signals whose amplitude and phase have beenchanged.

The transversal filter 10 as a first transversal filter is constitutedby subtraction-type first-order transversal filters 11 and 12 as firstsubtraction-type first-order transversal filters D, which are connectedin series with each other.

The transversal filter 20 as a second transversal filter is constitutedsuch that a subtraction-type first-order transversal filter 21 as afirst subtraction-type first-order transversal filter D is connected inseries with an addition-type first-order transversal filter 22 as afirst addition-type first-order transversal filter I.

The transversal filter 30 as a third transversal filter is constitutedby addition-type first-order transversal filters 31 and 32 as firstaddition-type first-order transversal filters I, which are connected inseries with each other.

A phase frequency computer 4 is constituted by division computationcircuitries 41 and 42, multiplication computation circuitry 43, n-throot computation circuitry 44, phase computation circuitry 45, andfrequency computation circuitry 46. The phase frequency computer 4performs phase computation and frequency computation that use thedigital signals X₁, X₂, and X₃ output by the transversal filters 10, 20,and 30, and thereby computes a phase θ_(X) and a frequency f_(X) of theinput digital signal X_(in).

The division computation circuitry 41 is a first division computationcircuitry that divides the output digital signal X₂ of the transversalfilter 20 by the output digital signal X₁ of the transversal filter 10,and outputs, to the multiplication computation circuitry 43, a divisioncomputation signal X₂/X₁ being a result of the division computation as afirst division computation signal.

The division computation circuitry 42 is a second division computationcircuitry that divides the output digital signal X₂ of the transversalfilter 20 by the output digital signal X₃ of the transversal filter 30,and outputs, to the multiplication computation circuitry 43, a divisioncomputation signal X₂/X₃ being a result of the division computation as asecond division computation signal.

The multiplication computation circuitry 43 performs a multiplicationcomputation between the division computation signal X₂/X₁ output by thedivision computation circuitry 41 and the division computation signalX₂/X₃ output by the division computation circuitry 42, and outputs, tothe n-th root computation circuitry 44, a multiplication computationsignal Y being a result of the multiplication computation.

The n-th root computation circuitry 44 is a root computation circuitrythat performs a root computation being an n-th root computation on theabsolute value of the multiplication computation signal Y output by themultiplication computation circuitry 43, and outputs, to the phasecomputation circuitry 45, an n-th root computation signal N being aresult of the n-th root computation.

The phase computation circuitry 45 computes a phase θ_(X) of the digitalsignal X_(in) by performing an arctangent computation on the n-th rootcomputation signal output by the n-th root computation circuitry 44, andperforming sign conversion on the result of the arctangent computationdepending on the sign of the division computation signal X₂/X₃ output bythe division computation circuitry 42.

Note that the n-th root computation circuitry 44 and the phasecomputation circuitry 45 may be constituted by, for example, combining amultiplier and a divider, etc. Alternatively, they may be constitutedby, for example, a memory or a table that temporarily storesintermediate results of an n-th root computation and an arctangentcomputation, and a computation circuitry such as a processor performingthe above-described computations.

The frequency computation circuitry 46 computes a frequency f_(X) of theinput digital signal X_(in) by using the phase θ_(X) computed by thephase computation circuitry 45.

FIGS. 2A to 2D are configuration diagrams illustrating subtraction-typefirst-order transversal filters and addition-type first-ordertransversal filters.

Specifically, FIG. 2A represents a first subtraction-type first-ordertransversal filter D, and FIG. 2B represents a second subtraction-typefirst-order transversal filter −D.

In addition, FIG. 2C represents a first addition-type first-ordertransversal filter I, and FIG. 2D represents a second addition-typefirst-order transversal filter −I.

Note that, in the example of FIG. 1, while the first subtraction-typefirst-order transversal filter D and the first addition-type first-ordertransversal filter I are used, the second subtraction-type first-ordertransversal filter −D and the second addition-type first-ordertransversal filter −I are not used.

The first subtraction-type first-order transversal filter D of FIG. 2Ais constituted by splitter circuitry 51, one-sampling time delayingcircuitry 52, and subtraction computation circuitry 53.

The splitter circuitry 51 is a first splitter circuitry that splits aninput digital signal X_(in) into two.

The one-sampling time delaying circuitry 52 is a first delayingcircuitry that delays one digital signal X_(in) split by the splittercircuitry 51 by one sampling time T_(s) (=1/f_(s)).

The subtraction computation circuitry 53 subtracts the digital signal,which has been delayed by the one-sampling time delaying circuitry 52,from the other digital signal X_(in) split by the splitter circuitry 51.

The second subtraction-type first-order transversal filter −D of FIG. 2Bis constituted by splitter circuitry 51, one-sampling time delayingcircuitry 52, and subtraction computation circuitry 54.

The subtraction computation circuitry 54 subtracts the other digitalsignal X_(in) split by the splitter circuitry 51 from a digital signalhaving been delayed by the one-sampling time delaying circuitry 52.

Note that the difference between the first subtraction-type first-ordertransversal filter D of FIG. 2A and the second subtraction-typefirst-order transversal filter −D of FIG. 2B is the sign of an inputsignal to the subtraction computation circuitries 53 and 54.Accordingly, the sign of an output signal from the firstsubtraction-type first-order transversal filter D of FIG. 2A is oppositeto that of an output signal from the second subtraction-type first-ordertransversal filter −D of FIG. 2B.

The first addition-type first-order transversal filter I of FIG. 2C isconstituted by splitter circuitry 61, one-sampling time delayingcircuitry 62, and addition computation circuitry 63.

The splitter circuitry 61 is a second splitter circuitry that splits aninput digital signal X_(in) into two.

The one-sampling time delaying circuitry 62 is a second delayingcircuitry that delays one digital signal X_(in) split by the splittercircuitry 61 by one sampling time T_(s).

The addition computation circuitry 63 adds the digital signal delayed bythe one-sampling time delaying circuitry 62 to the other digital signalX_(in) split by the splitter circuitry 61.

The second addition-type first-order transversal filter −I of FIG. 2D isconstituted by splitter circuitry 61, one-sampling time delayingcircuitry 62, and addition computation circuitry 64.

The addition computation circuitry 64 receives a digital signal obtainedby reversing a sign of the digital signal having been delayed by theone-sampling time delaying circuitry 62, and also receives a digitalsignal obtained by reversing a sign of the other digital signal X_(in)split by the splitter circuitry 61. After that, the addition computationcircuitry 64 adds the received former digital signal to the receivedlatter digital signal X_(in).

Note that the difference between the first addition-type first-ordertransversal filter I of FIG. 2C and the second addition-type first-ordertransversal filter −I of FIG. 2D is the sign of signals input to theaddition computation circuitries 63 and 64. Accordingly, the sign of anoutput signal from the first addition-type first-order transversalfilter I of FIG. 2C is opposite to that of an output signal from thesecond addition-type first-order transversal filter −I of FIG. 2D.

Next, operation will be described.

It is assumed that a digital signal X_(in)[n·T_(s)] is input to thetransversal filters 10, 20, and 30 of the filter circuitry 1 at adiscrete time n·T_(s).

The following equation (1) represents the time waveform of the digitalsignal X_(in)[n·T_(s)].

X _(in) [n·T _(s)]=α·cos(Δθ+Σθ_(n-1))  (1)

In the equation (1), α is the amplitude factor of X_(in), Δθ is theamount of change in phase during one sampling time, and Σθ_(n-1) is anintegrated value of phases at discrete-times from zero to n−1.

In the transversal filter 10, the subtraction-type first-ordertransversal filters 11 and 12 being the first subtraction-typefirst-order transversal filter D shown in FIG. 2A are connected inseries with each other. Thus, by receiving a digital signalX_(in)[n·T_(s)], the transversal filter 10 changes amplitude and a phaseof the digital signal X_(in)[n·T_(s)], and outputs, to the phasefrequency computer 4, a resulting digital signal X₁[n·T_(s)] whoseamplitude and phase have been changed.

Specifically, by receiving a digital signal X_(in)[n·T_(s)], thesubtraction-type first-order transversal filter 11 of the transversalfilter 10 outputs, to the subtraction-type first-order transversalfilter 12, a digital signal X₁′[n·T_(s)] obtained by the followingequation (2).

$\begin{matrix}\begin{matrix}{{X_{1}^{\prime}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {{X_{in}\left\lbrack {n \cdot T_{s}} \right\rbrack} - {X_{in}\left\lbrack {\left( {n - 1} \right) \cdot T_{s}} \right\rbrack}}} \\{= {{\alpha \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 1}} \right)}} - {\alpha \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}} \\{= {{\alpha \cdot {\cos \left( {{2 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}} - {\alpha \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}} \\{= {{- 2} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {{1.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}}}\end{matrix} & (2)\end{matrix}$

The subtraction-type first-order transversal filter 12 of thetransversal filter 10 receives the digital signal X₁′[n·T_(s)] from thesubtraction-type first-order transversal filter 11, and outputs, to thephase frequency computer 4, a digital signal X₁[n·T_(s)] obtained by thefollowing equation (3).

$\begin{matrix}\begin{matrix}{{X_{1}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {{X_{1}^{\prime}\left\lbrack {n \cdot T_{s}} \right\rbrack} - {X_{1}^{\prime}\left\lbrack {\left( {n - 1} \right) \cdot T_{s}} \right\rbrack}}} \\{= {{{- 2} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {{1.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}} +}} \\{{2 \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {{0.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}}} \\{= {{- 2} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot \begin{bmatrix}{{\sin \left( {{1.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)} -} \\{\sin \left( {{0.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}\end{bmatrix}}} \\{= {{- 2} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot \left\lbrack {2 \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}} \right\rbrack}} \\{= {{- 4} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}\end{matrix} & (3)\end{matrix}$

In the transversal filter 20, the subtraction-type first-ordertransversal filter 21 being the first subtraction-type first-ordertransversal filter D shown in FIG. 2A is connected in series with theaddition-type first-order transversal filter 22 being the firstaddition-type first-order transversal filter I shown in FIG. 2C. Thus,by receiving a digital signal X_(in)[n·T_(s)], the transversal filter 20changes amplitude and a phase of the digital signal X_(in)[n·T_(s)], andoutputs, to the phase frequency computer 4, a resulting digital signalX₂[n·T_(s)] whose amplitude and phase have been changed.

Specifically, by receiving a digital signal X_(in)[n·T_(s)], thesubtraction-type first-order transversal filter 21 of the transversalfilter 20 outputs, to the addition-type first-order transversal filter22, a digital signal X₂′[n·T_(s)] obtained by the following equation(4).

$\begin{matrix}\begin{matrix}{{X_{2}^{\prime}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {{X_{in}\left\lbrack {n \cdot T_{s}} \right\rbrack} - {X_{in}\left\lbrack {\left( {n - 1} \right) \cdot T_{s}} \right\rbrack}}} \\{= {{\alpha \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 1}} \right)}} - {\alpha \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}} \\{= {{\alpha \cdot {\cos \left( {{2 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}} - {\alpha \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}} \\{= {{- 2} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {{1.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}}}\end{matrix} & (4)\end{matrix}$

The addition-type first-order transversal filter 22 of the transversalfilter 20 receives the digital signal X₂′[n·T_(s)] from thesubtraction-type first-order transversal filter 21, and outputs, to thephase frequency computer 4, a digital signal X₂[n·T_(s)] obtained by thefollowing equation (5).

$\begin{matrix}\begin{matrix}{{X_{2}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {{X_{2}^{\prime}\left\lbrack {n \cdot T_{s}} \right\rbrack} - {X_{2}^{\prime}\left\lbrack {\left( {n - 1} \right) \cdot T_{s}} \right\rbrack}}} \\{= {{{- 2} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {{1.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}} -}} \\{{2 \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {{0.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}}} \\{= {{- 2} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot \begin{bmatrix}{{\sin \left( {{1.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)} +} \\{\sin \left( {{0.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}\end{bmatrix}}} \\{= {{- 2} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot \left\lbrack {2 \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}} \right\rbrack}} \\{= {{- 4} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}\end{matrix} & (5)\end{matrix}$

In the transversal filter 30, the addition-type first-order transversalfilters 31 and 32 being the first addition-type first-order transversalfilter I shown in FIG. 2C are connected in series with each other. Thus,by receiving a digital signal X_(in)[n·T_(s)], the transversal filter 30changes amplitude and a phase of the digital signal X_(in)[n·T_(s)] andoutputs, to the phase frequency computer 4, a resulting digital signalX₃[n·T_(s)] whose amplitude and phase have been changed.

Specifically, by receiving a digital signal X_(in)[n·T_(s)], theaddition-type first-order transversal filter 31 of the transversalfilter 30 outputs, to the addition-type first-order transversal filter32, a digital signal X₃′[n·T_(s)] obtained by the following equation(6).

$\begin{matrix}\begin{matrix}{{X_{3}^{\prime}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {{X_{in}\left\lbrack {n \cdot T_{s}} \right\rbrack} + {X_{in}\left\lbrack {\left( {n - 1} \right) \cdot T_{s}} \right\rbrack}}} \\{= {{\alpha \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 1}} \right)}} + {\alpha \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}} \\{= {{\alpha \cdot {\cos \left( {{2 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}} + {\alpha \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}} \\{= {2 \cdot \alpha \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {{1.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}}}\end{matrix} & (6)\end{matrix}$

The addition-type first-order transversal filter 32 of the transversalfilter 30 receives the digital signal X₃′[n·T_(s)] from theaddition-type first-order transversal filter 31, and outputs, to thephase frequency computer 4, a digital signal X₃[n·T_(s)] obtained by thefollowing equation (7).

$\begin{matrix}\begin{matrix}{{X_{3}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {{X_{3}^{\prime}\left\lbrack {n \cdot T_{s}} \right\rbrack} + {X_{3}^{\prime}\left\lbrack {\left( {n - 1} \right) \cdot T_{s}} \right\rbrack}}} \\{= {{2 \cdot \alpha \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {{1.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}} +}} \\{{2 \cdot \alpha \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {{0.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}}} \\{= {2 \cdot \alpha \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot \begin{bmatrix}{{\cos \left( {{1.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)} +} \\{\cos \left( {{0.5 \cdot {\Delta\theta}} + {\Sigma\theta}_{n - 2}} \right)}\end{bmatrix}}} \\{= {4 \cdot \alpha \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}\end{matrix} & (7)\end{matrix}$

The phase frequency computer 4 receives the digital signals X₁[n·T_(s)],X₂[n·T_(s)], and X₃[n·T_(s)] from the transversal filters 10, 20, and30, and computes a phase θ_(X)[n·T_(s)] and a frequency f_(X)[n·T_(s)]of the input digital signal X_(in) by performing phase computation andfrequency computation using the received digital signals X₁[n·T_(s)],X₂[n·T_(s)], and X₃[n·T_(s)].

Specifically, by receiving the digital signals X₁[n·T_(s)] andX₂[n·T_(s)] from the transversal filters 10 and 20, the divisioncomputation circuitry 41 divides the digital signal X₂[n·T_(s)] by thedigital signal X₁[n·T_(s)], as shown in the following equation (8), andoutputs, to the multiplication computation circuitry 43, a divisioncomputation signal X₂[n·T_(s)]/X₁[n·T_(s)] being the result of thedivision computation.

$\begin{matrix}\begin{matrix}{\frac{X_{2}\left\lbrack {n \cdot T_{s}} \right\rbrack}{X_{1}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {\left\lbrack {{- 4} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}} \right\rbrack/}} \\{\left\lbrack {{- 4} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}} \right\rbrack} \\{= {{\cot \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\tan \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}\end{matrix} & (8)\end{matrix}$

By receiving the digital signals X₂[n·T_(s)] and X₃[n·T_(s)] from thetransversal filters 20 and 30, the division computation circuitry 42divides the digital signal X₂[n·T_(s)] by the digital signalX₃[n·T_(s)], as shown in the following equation (9), and outputs, to themultiplication computation circuitry 43, a division computation signalX₂[n·T_(s)]/X₃[n·T_(s)] being the result of the division computation.

$\begin{matrix}\begin{matrix}{\frac{X_{2}\left\lbrack {n \cdot T_{s}} \right\rbrack}{X_{3}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {\left\lbrack {{- 4} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}} \right\rbrack/}} \\{\left\lbrack {4 \cdot \alpha \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}} \right\rbrack} \\{= {{- {\tan \left( {0.5 \cdot {\Delta\theta}} \right)}} \cdot {\tan \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}\end{matrix} & (9)\end{matrix}$

The multiplication computation circuitry 43 receives the divisioncomputation signals X₂[n·T_(s)]/X₁[n·T_(s)] and X₂[n·T_(s)]/X₃[n·T_(s)]output by the division computation circuitries 41 and 42. Themultiplication computation circuitry 43 multiplies the divisioncomputation signal X₂[n·T_(s)]/X₁[n·T_(s)] by the division computationsignal X₂[n·T_(s)]/X₃[n·T_(s)], as shown in the following equation (10),and outputs, to the n-th root computation circuitry 44, a multiplicationcomputation signal Y[n·T_(s)] being the result of the multiplicationcomputation.

$\begin{matrix}\begin{matrix}{{Y\left\lbrack {n \cdot T_{s}} \right\rbrack} = {\left( {{X_{2}\left\lbrack {n \cdot T_{s}} \right\rbrack}/{X_{1}\left\lbrack {n \cdot T_{s}} \right\rbrack}} \right) \cdot \left( {{X_{2}\left\lbrack {n \cdot T_{s}} \right\rbrack}/{X_{3}\left\lbrack {n \cdot T_{s}} \right\rbrack}} \right)}} \\{= {- {\tan^{2}\left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}}\end{matrix} & (10)\end{matrix}$

The n-th root computation circuitry 44 receives the multiplicationcomputation signal Y[n·T_(s)] from the multiplication computationcircuitry 43. The n-th root computation circuitry 44 performs an n-throot computation on the absolute value of the received multiplicationcomputation signal Y[n·T_(s)], and outputs, to the phase computationcircuitry 45, an n-th root computation signal N[n·T_(s)] being theresult of the n-th root computation.

N[n·T _(s)]=tan(Δθ+Σθ_(n-2))  (11)

Here, since n for the n-th root computation is 0.5, N[n·T_(s)] is[|Y[n·T_(s)]|]^(0.5).

After receiving the n-th root computation signal N[n·T_(s)] from then-th root computation circuitry 44, the phase computation circuitry 45performs an arctangent computation on the n-th root computation signalN[n·T_(s)] according to following equation (12). The phase computationcircuitry 45 further performs sign conversion on the result of thearctangent computation depending on the sign of the division computationsignal X₂[n·T_(s)]/X₃[n·T_(s)] output by the division computationcircuitry 42, and thereby computes a phase θ_(X)[n·T_(s)] of the digitalsignal X_(in).

Specifically, when the sign of the division computation signalX₂[n·T_(s)]/X₃[n·T_(s)] is positive, the sign of the phaseθ_(X)[n·T_(s)] of the digital signal X_(in) is also positive, and whenthe sign of the division computation signal X₂[n·T_(s)]/X₃[n·T_(s)] isnegative, the sign of the phase θ_(X)[n·T_(s)] of the digital signalX_(in) is also negative.

$\begin{matrix}\begin{matrix}{{\theta_{X}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {\tan^{- 1}\left( {{N\left\lbrack {n \cdot T_{s}} \right\rbrack}} \right)}} \\{= {- {\tan^{1}\left( {{\tan \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}} \right)}}}\end{matrix} & (12)\end{matrix}$

The example is disclosed here, in which the phase computation circuitry45 performs sign conversion on the result of the arctangent computationdepending on the sign of the division computation signalX₂[n·T_(s)]/X₃[n·T_(s)] output by the division computation circuitry 42.Alternatively, the phase computation circuitry 45 may perform signconversion on the result of the arctangent computation depending on thesign of the division computation signal X₂[n·T_(s)]/X₁[n·T_(s)] outputby the division computation circuitry 41.

When the transversal filters 10, 20, and 30 in the filter circuitry 1have the configurations shown in FIG. 1, the sign of the divisioncomputation signal X₂[n·T_(s)]/X₁[n·T_(s)] output by the divisioncomputation circuitry 41 is the same as that of the division computationsignal X₂[n·T_(s)]/X₃[n·T_(s)] output by the division computationcircuitry 42.

After the phase θ_(X)[n·T_(s)] of the digital signal X_(in) is computedby the phase computation circuitry 45, the frequency computationcircuitry 46 computes a frequency f_(X)[n·T_(s)] of the input digitalsignal X_(in) by using the phase θ_(X)[n·T_(s)] of the digital signalX_(in), as shown in the following equation (13).

f _(X) [n·T _(s)]={θ_(X) [n·T _(s)]−θ_(X)[(n−1)·T _(s) ]}·f_(s)/(2π)  (13)

In the Embodiment 1, the phase frequency computer 4 is able to obtain bythe equations (12) and (13) the phase θ_(X)[n·T_(s)] and frequencyf_(X)[n·T_(s)] of the digital signal X_(in) without performing a Hilberttransformation.

In addition, since the number of stages of delay circuitry used by thetransversal filters 10, 20, and 30 is two, the delay time resulting fromdetection is as short as two sampling times and thus a short-pulse inputsignal can be detected.

The Embodiment 1 represents that the division computation circuitry 41computes a division computation signal X₂[n·T_(s)]/X₁[n·T_(s)] and thedivision computation circuitry 42 computes a division computation signalX₂[n·T_(s)]/X₃[n·T_(s)]. Alternatively, the division computationcircuitry 41 may compute a division computation signalX₁[n·T_(s)]/X₂[n·T_(s)] and the division computation circuitry 42 maycompute a division computation signal X₃[n·T_(s)]/X₂[n·T_(s)].

In this case, an n-th root computation signalN[n·T_(s)]=[|Y[n·T_(s)]|]^(0.5) output by the n-th root computationcircuitry 44 is given by the following equation (14).

$\begin{matrix}\begin{matrix}{{N\left\lbrack {n \cdot T_{s}} \right\rbrack} = \left\lbrack {{Y\left\lbrack {n \cdot T_{s}} \right\rbrack}} \right\rbrack^{0.5}} \\{= {\cot \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}}\end{matrix} & (14)\end{matrix}$

Here, in accordance with the mathematical formula“cot⁻¹(X)=−tan⁻¹(X)+π/2”, an arctangent computation is performed on avalue obtained by the equation (14), and π/2 is added to the result ofthe arctangent computation whose sign is reversed. As a result, thephase θ_(X)[n·T_(s)] of the digital signal X_(in) has the same value asthat obtained in equation (12).

As is clear from the above description, according to the Embodiment 1,it is constituted such that the filter circuitry 1 including thetransversal filters 10, 20, and 30 connected in parallel to each otheris provided, the transversal filters 10, 20, and 30 changing theamplitude and phase of an input digital signal X_(in)[n·T_(s)] andoutputting different digital signals X₁[n·T_(s)], X₂[n·T_(s)], andX₃[n·T_(s)] as respective resulting digital signals whose amplitude andphase have been changed; and the phase frequency computer 4 performsphase computation and frequency computation that use the digital signalsX₁[n·T_(s)], X₂[n·T_(s)], and X₃[n·T_(s)] output by the transversalfilters 10, 20, and 30, and thereby computes the phase θ_(X)[n·T_(s)]and frequency f_(X)[n·T_(s)] of the input digital signalX_(in)[n·T_(s)]. Thus, advantageous effects are achieved such that, evenif a digital signal X_(in)[n·T_(s)] to be input is a short-pulse signal,a phase θ_(X)[n·T_(s)] and a frequency f_(X)[n·T_(s)] can be detected,and increase in circuitry size and increase in power consumption, whichmay be caused by increase in the number of stages of delay circuitry,can be suppressed.

The Embodiment 1 represents an example, in which in the transversalfilter 10 the subtraction-type first-order transversal filters 11 and 12being the first subtraction-type first-order transversal filter D shownin FIG. 2A are connected in series with each other, in the transversalfilter 20 the subtraction-type first-order transversal filter 21 beingthe first subtraction-type first-order transversal filter D shown inFIG. 2A is connected in series with the addition-type first-ordertransversal filter 22 being the first addition-type first-ordertransversal filter I shown in FIG. 2C, and in the transversal filter 30the addition-type first-order transversal filters 31 and 32 being thefirst addition-type first-order transversal filter I shown in FIG. 2Care connected in series with each other.

Note, however, that this is simply one example. The transversal filters10, 20, and 30 may have any combination of types of first-ordertransversal filters to be used.

For example, while the second subtraction-type first-order transversalfilter −D shown in FIG. 2B may be used as the subtraction-typefirst-order transversal filters 11, 12, and 21, the second addition-typefirst-order transversal filter −I shown in FIG. 2D may be used as theaddition-type first-order transversal filters 22, 31, and 32, andthereby the same advantageous effects can be achieved.

Note that the result of sign conversion performed by the phasecomputation circuitry 45 is reversed depending on the combination offirst-order transversal filters to be used.

Embodiment 2

The above-described Embodiment 1 represents that the phase frequencycomputer 4 performs a multiplication computation by the multiplicationcomputation circuitry 43 after performing a division computation by eachof the division computation circuitries 41 and 42. However, the phasefrequency computer 4 may perform a division computation after amultiplication computation.

FIG. 3 is a configuration diagram illustrating a phase frequencydetection device of Embodiment 2 of the invention. In FIG. 3, the samereference signs as those in FIG. 1 indicate the same or correspondingportions and thus description thereof is omitted.

Multiplication computation circuitry 71 is first multiplicationcomputation circuitry that performs a multiplication computation betweena digital signal X₁[n·T_(s)] output by a transversal filter 10 and adigital signal X₃[n·T_(s)] output by a transversal filter 30, andoutputs a resulting signal X₁[n·T_(s)]·X₃[n·T_(s)] of the multiplicationcomputation as a first multiplication computation signal.

Multiplication computation circuitry 72 is second multiplicationcomputation circuitry that performs a square multiplication on a digitalsignal X₂[n·T_(s)] output by a transversal filter 20 and outputs theresulting signal X₂[n·T_(s)]·X₂[n·T_(s)] of the square multiplication asa second multiplication computation signal.

Division computation circuitry 73 divides the resulting signalX₂[n·T_(s)]·X₂[n·T_(s)] of the square multiplication coming from themultiplication computation circuitry 72 by the resulting signalX₁[n·T_(s)]·X₃[n·T_(s)] of the multiplication computation coming fromthe multiplication computation circuitry 71. After that, the computationcircuitry 73 outputs a resulting signal(X₂[n·T_(s)]·X₂[n·T_(s)])/(X₁[n·T_(s)]·X₃[n·T_(s)]) of the divisioncomputation as a division computation signal to an n-th root computationcircuitry 44.

As shown in FIG. 3, even when the phase frequency computer 4 performs adivision computation by the division computation circuitry 73 afterperforming a multiplication computation by each of the multiplicationcomputation circuitries 71 and 72, the same value as that shown inequation (10) is output to the n-th root computation circuitry 44. Thus,the same advantageous effects as those in the above-described Embodiment1 can be achieved.

Embodiment 3

The above-described Embodiment 1 represents that the filter circuitry 1is constituted by the three transversal filters 10, 20, and 30, whichare connected in parallel to each other. Alternatively, the filtercircuitry may be constituted by two transversal filters 10 and 30, whichare connected in parallel to each other.

FIG. 4 is a configuration diagram illustrating a phase frequencydetection device of Embodiment 3 of the invention. In FIG. 4, the samereference signs as those in FIG. 1 indicate the same or correspondingportions and thus description thereof is omitted.

In the Embodiment 3, a transversal filter 10 serves as a firsttransversal filter, and a transversal filter 30 serves as a secondtransversal filter.

Division computation circuitry 81 divides a digital signal X₁ comingfrom the transversal filter 10 by a digital signal X₃ coming from thetransversal filter 30, and outputs, to n-th root computation circuitry82, a division computation signal X₁/X₃ being the result of the divisioncomputation.

The n-th root computation circuitry 82 is root computation circuitrythat performs an n-th root computation on the absolute value of thedivision computation signal X₁/X₃ output by the division computationcircuitry 81, and outputs, to frequency computation circuitry 83, ann-th root computation signal N being the result of the n-th rootcomputation.

The frequency computation circuitry 83 computes a frequency f_(X) of aninput digital signal X_(in) by using the n-th root computation signal Noutput by the n-th root computation circuitry 82.

Phase computation circuitry 84 computes a phase θ_(X) of the inputdigital signal X_(in) by using the frequency f_(X) computed by thefrequency computation circuitry 83.

Next, operation will be described.

It is assumed that a digital signal X_(in)[n·T_(s)] is input to thetransversal filters 10 and 30 in the filter circuitry 1 at discrete timen·T_(s) in the same manner as the above-described Embodiment 1.

In the transversal filter 10, the subtraction-type first-ordertransversal filters 11 and 12, each of which is the firstsubtraction-type first-order transversal filter D shown in FIG. 2A, areconnected in series with each other. Thus, by inputting a digital signalX_(in)[n·T_(s)] to the transversal filter 10, the transversal filter 10changes the amplitude and phase of the digital signal X_(in)[n·T_(s)]and outputs, to a phase frequency computer 4, a resulting digital signalX₁[n·T_(s)] whose amplitude and phase have been changed.

Specifically, after receiving the digital signal X_(in)[n·T_(s)], thesubtraction-type first-order transversal filter 11 of the transversalfilter 10 outputs a digital signal X₁′[n·T_(s)] according to theabove-described equation (2) to the subtraction-type first-ordertransversal filter 12.

The subtraction-type first-order transversal filter 12 of thetransversal filter 10 receives the digital signal X₁′[n·T_(s)] comingfrom the subtraction-type first-order transversal filter 11 and outputsa digital signal X₁[n·T_(s)] according to the above-described equation(3) to the phase frequency computer 4.

In the transversal filter 30, the addition-type first-order transversalfilters 31 and 32, each of which are the first addition-type first-ordertransversal filter I shown in FIG. 2C, are connected in series with eachother. Thus, by inputting a digital signal X_(in)[n·T_(s)] to thetransversal filter 30, the transversal filter 30 changes the amplitudeand phase of the digital signal X_(in)[n·T_(s)] and outputs, to thephase frequency computer 4, a resulting digital signal X₃[n·T_(s)] whoseamplitude and phase have been changed.

Specifically, after receiving the digital signal X_(in)[n·T_(s)], theaddition-type first-order transversal filter 31 of the transversalfilter 30 outputs a digital signal X₃′[n·T_(s)] according to theabove-described equation (6) to the addition-type first-ordertransversal filter 32.

The addition-type first-order transversal filter 32 of the transversalfilter 30 receives the digital signal X₃′[n·T_(s)] coming from theaddition-type first-order transversal filter 31 and outputs a digitalsignal X₃[n·T_(s)] according to the above-described equation (7) to thephase frequency computer 4.

After receiving the digital signals X₁[n·T_(s)] and X₃[n·T_(s)] comingfrom the transversal filters 10 and 30, the phase frequency computer 4performs phase computation and frequency computation using the digitalsignals X₁[n·T_(s)] and X₃[n·T_(s)], and thereby computes a phaseθ_(X)[n·T_(s)] and a frequency f_(X)[n·T_(s)] of the input digitalsignal X_(in).

Specifically, by receiving the digital signals X₁[n·T_(s)] andX₃[n·T_(s)] from the transversal filters 10 and 30, the divisioncomputation circuitry 81 of the phase frequency computer 4 divides, asshown in the following equation (15), the digital signal X₁[n·T_(s)] bythe digital signal X₃[n·T_(s)] and outputs to the n-th root computationcircuitry 82 a division computation signal X₁[n·T_(s)]/X₃[n·T_(s)] beingthe result of the division computation.

$\begin{matrix}\begin{matrix}{\frac{X_{1}\left\lbrack {n \cdot T_{s}} \right\rbrack}{X_{3}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {\left\lbrack {{- 4} \cdot \alpha \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\sin \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}} \right\rbrack/}} \\{\left\lbrack {4 \cdot \alpha \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {0.5 \cdot {\Delta\theta}} \right)} \cdot {\cos \left( {{\Delta\theta} + {\Sigma\theta}_{n - 2}} \right)}} \right\rbrack} \\{= {- {\tan \left( {0.5 \cdot {\Delta\theta}} \right)}}}\end{matrix} & (15)\end{matrix}$

The n-th root computation circuitry 82 receives the division computationsignal X₁[n·T_(s)]/X₃[n·T_(s)] from the division computation circuitry81. The n-th root computation circuitry 82 performs an n-th rootcomputation on the absolute value of the division computation signalX₁[n·T_(s)]/X₃[n·T_(s)] and outputs, to the frequency computationcircuitry 83, an n-th root computation signal N[n·T_(s)] being theresult of the n-th root computation.

N[n·T _(s)]=tan(0.5·Δθ)  (16)

Here, since n in the n-th root computation is 0.5, N[n·T_(s)] is[|−tan²(0.5·Δθ)|]^(0.5).

The frequency computation circuitry 83 receives the n-th rootcomputation signal N[n·T_(s)] from the n-th root computation circuitry82 and performs an arctangent computation on the n-th root computationsignal N[n·T_(s)] according to the following equation (17).

$\begin{matrix}\begin{matrix}{{\tan^{- 1}\left( {{N\left\lbrack {n \cdot T_{s}} \right\rbrack}} \right)} = {\tan^{- 1}\left( {{\tan \left( {0.5 \cdot {\Delta\theta}} \right)}} \right)}} \\{= {0.5 \cdot {\Delta\theta}}}\end{matrix} & (17)\end{matrix}$

Subsequently, the frequency computation circuitry 83 computes afrequency f_(X)[n·T_(s)] of the digital signal X_(in)[n·T_(s)] accordingto the following equation (18) by using 0.5·Δθ being the result of thearctangent computation for the n-th root computation signal N[n·T_(s)].

$\begin{matrix}\begin{matrix}{{f_{X}\left\lbrack {n \cdot T_{s}} \right\rbrack} = {\left( {0.5 \cdot {\Delta\theta}} \right) \cdot 2 \cdot {f_{s}/\left( {2\pi} \right)}}} \\{= {{\Delta\theta} \cdot {f_{s}/\left( {2\pi} \right)}}}\end{matrix} & (18)\end{matrix}$

Note that, according to the equation (18), the amount of change in phaseΔθ for one sampling time always has a positive value as with thefrequency f_(X)[n·T_(s)]. Hence, phase sign conversion, such asdescribed in the above-described Embodiment 1, is not required.

After the frequency f_(X)[n·T_(s)] of the digital signal X_(in)[n·T_(s)]is computed by frequency computation circuitry 83, the phase computationcircuitry 84 computes a phase θ_(X)[n·T_(s)] of the digital signalX_(in)[n·T_(s)], according to the following equation (19), by using thefrequency f_(X)[n·T_(s)] of the digital signal X_(in)[n·T_(s)].

θ_(X) [n·T _(s) ]=Σ[f _(X) [n·T _(s)]·(2π)/f _(s)]  (19)

In the Embodiment 3, by using the equations (18) and (19), the phasefrequency computer 4 is able to detect the phase θ_(X)[n·T_(s)] andfrequency f_(X)[n·T_(s)] of the digital signal X_(in) without performinga Hilbert transformation.

In addition, since the number of stages of delay circuitry used by thetransversal filters 10 and 30 is two, the delay time resulting fromdetection is as short as two sampling times and thus a short-pulse inputsignal can be detected.

The Embodiment 3 represents that the division computation circuitry 81computes a division computation signal X₁[n·T_(s)]/X₃[n·T_(s)].Alternatively, the division computation circuitry 81 may compute adivision computation signal X₃[n·T_(s)]/X₁[n·T_(s)].

Note that, in this case, it is required to add π/2 to the result of anarctangent computation for an n-th root computation signal N[n·T_(s)].By the addition of π/2, the same value as that obtained in the equation(17) is obtained.

As is clear from the above, according to the Embodiment 3, the filtercircuitry 1 is constituted by the transversal filters 10 and 30connected in parallel to each other, where the transversal filters 10and 30 change amplitude and phase of an input digital signalX_(in)[n·T_(s)] and output different digital signals X₁[n·T_(s)] andX₃[n·T_(s)] as respective resulting digital signals whose amplitude andphase have been changed. Further, the phase frequency computer 4performs phase computation and frequency computation using the digitalsignals X₁[n·T_(s)] and X₃[n·T_(s)] output by the transversal filters 10and 30, and thereby computes the phase θ_(X)[n·T_(s)] and frequencyf_(X)[n·T_(s)] of the input digital signal X_(in)[n·T_(s)]. Thus,advantageous effects are provided that even if a digital signalX_(in)[n·T_(s)] to be input is a short-pulse signal, a phaseθ_(X)[n·T_(s)] and a frequency f_(X)[n·T_(s)] can be detected, andincrease in circuitry size and increase in power consumption whichresult from increase in the number of stages of delay circuitry can besuppressed.

The Embodiment 3 represents an example that the transversal filter 10 isconstituted by the subtraction-type first-order transversal filters 11and 12, which are the first subtraction-type first-order transversalfilter D shown in FIG. 2A, are connected in series with each other, andthe transversal filter 30 is constituted by the addition-typefirst-order transversal filters 31 and 32, which are the firstaddition-type first-order transversal filter I shown in FIG. 2C, areconnected in series with each other.

Note, however, that this is simply one example. The transversal filters10 and 30 may have any combination of types of first-order transversalfilters to be used.

For example, while the second subtraction-type first-order transversalfilter −D shown in FIG. 2B may be used as the subtraction-typefirst-order transversal filters 11 and 12, the second addition-typefirst-order transversal filter −I shown in FIG. 2D may be used as theaddition-type first-order transversal filters 31 and 32, and thereby thesame advantageous effects can be achieved.

Embodiment 4

FIG. 5 is a configuration diagram illustrating filter circuitry 1 of aphase frequency detection device of Embodiment 4 of the invention. InFIG. 5, the same reference signs as those in FIG. 1 indicate the same orcorresponding portions.

The above-described Embodiment 1 represents that the transversal filter20 is constituted by the subtraction-type first-order transversal filter21 being the first subtraction-type first-order transversal filter Dshown in FIG. 2A and the addition-type first-order transversal filter 22being the first addition-type first-order transversal filter I shown inFIG. 2C, which are connected in series with each other. Alternatively,as shown in FIG. 5, a transversal filter 20 may be constituted by anaddition-type first-order transversal filter 22 to which is input adigital signal output by a subtraction-type first-order transversalfilter 11 of a transversal filter 10. The addition-type first-ordertransversal filter 22 is the first addition-type first-order transversalfilter I shown in FIG. 2C.

In the case of FIG. 5, a digital signal X₁′[n·T_(s)] output by thesubtraction-type first-order transversal filter 11 of the transversalfilter 10 indicates the same value as a digital signal X₂′[n·T_(s)]output by the subtraction-type first-order transversal filter 21 of thetransversal filter 20 of FIG. 1. Therefore, a digital signal X₂[n·T_(s)]output by the addition-type first-order transversal filter 22 of thetransversal filter 20 indicates the same one as that in theabove-described Embodiment 1.

Accordingly, the computation of a phase frequency computer 4 is the sameas that in the above-described Embodiment 1, and thus, the sameadvantageous effects as those in the above-described Embodiment 1 can beachieved.

In addition, since the subtraction-type first-order transversal filter21 is not required for the transversal filter 20, the circuitry size canbe reduced over the above-described Embodiment 1.

Embodiment 5

FIG. 6 is a configuration diagram illustrating filter circuitry 1 of aphase frequency detection device of Embodiment 5 of the invention. InFIG. 6, the same reference signs as those in FIG. 1 indicate the same orcorresponding portions.

The above-described Embodiment 1 represents that the transversal filter20 is constituted by the subtraction-type first-order transversal filter21 being the first subtraction-type first-order transversal filter Dshown in FIG. 2A and the addition-type first-order transversal filter 22being the first addition-type first-order transversal filter I shown inFIG. 2C, which are connected in series with each other. Alternatively,as shown in FIG. 6, a transversal filter 20 may be constituted by asubtraction-type first-order transversal filter 21 to which is input adigital signal output by an addition-type first-order transversal filter31 of a transversal filter 30. The subtraction-type first-ordertransversal filter 21 is the first subtraction-type first-ordertransversal filter D shown in FIG. 2A.

In the case of FIG. 6, the transversal filter 20 is constituted by onlythe subtraction-type first-order transversal filter 21. Since a digitalsignal output by the addition-type first-order transversal filter 31 ofthe transversal filter 30 is input to the subtraction-type first-ordertransversal filter 21, the transversal filter 20 is substantiallyequivalent to a transversal filter in which the addition-typefirst-order transversal filter 31 is connected in series with thesubtraction-type first-order transversal filter 21.

The connection order of the addition-type first-order transversal filter31 and the subtraction-type first-order transversal filter 21 composingthe above-described transversal filter is opposite to that of thesubtraction-type first-order transversal filter 21 and the addition-typefirst-order transversal filter 22 in the transversal filter 20 ofFIG. 1. However, even if the connection order is opposite, digitalsignals to be finally output are the same.

Hence, a digital signal X₂[n·T_(s)] to be output by the transversalfilter 20 of FIG. 6, which is constituted by only the subtraction-typefirst-order transversal filter 21, indicates the same value as a digitalsignal X₂[n·T_(s)] to be output by the transversal filter 20 of FIG. 1.

Therefore, the computation of a phase frequency computer 4 is the sameas that in the above-described Embodiment 1, and thus, the sameadvantageous effects as those in the above-described Embodiment 1 can beobtained.

In addition, since the transversal filter 20 does not require theaddition-type first-order transversal filter 22, the circuitry size canbe reduced over the above-described Embodiment 1.

Embodiment 6

FIG. 7 is a configuration diagram illustrating filter circuitry 1 of aphase frequency detection device of Embodiment 6 of the invention. InFIG. 7, the same reference signs as those in FIG. 1 indicate the same orcorresponding portions.

The above-described Embodiment 1 represents that an input-sidefirst-order transversal filter in the transversal filter 20 is thesubtraction-type first-order transversal filter 21, an output-sidefirst-order transversal filter is the addition-type first-ordertransversal filter 22, and the transversal filter 30 is constituted bythe addition-type first-order transversal filters 31 and 32, each ofwhich is the first addition-type first-order transversal filter I shownin FIG. 2C, are connected in series with each other.

In the Embodiment 6, as shown in FIG. 7, the order of a subtraction-typefirst-order transversal filter 21 and an addition-type first-ordertransversal filter 22 that compose a transversal filter 20 is switchedso that the addition-type first-order transversal filter 22 can serve asan input-side first-order transversal filter while the subtraction-typefirst-order transversal filter 21 can serve as an output-sidefirst-order transversal filter.

In addition, a transversal filter 30 is constituted by an addition-typefirst-order transversal filter 32 to which is input a digital signaloutput by the addition-type first-order transversal filter 22 in thetransversal filter 20. The addition-type first-order transversal filter32 is the first addition-type first-order transversal filter I shown inFIG. 2C.

In the case of FIG. 7, the connection order of the addition-typefirst-order transversal filter 22 and the subtraction-type first-ordertransversal filter 21 composing the transversal filter 20 is opposite tothat of the subtraction-type first-order transversal filter 21 and theaddition-type first-order transversal filter 22 that compose thetransversal filter 20 of FIG. 1. However, even if the connection orderis opposite, digital signals X₂[n·T_(s)] to be finally output are thesame.

In addition, a digital signal X₂′[n·T_(s)] to be output by theaddition-type first-order transversal filter 22 in the transversalfilter 20 indicates the same value as a digital signal X₃′[n·T_(s)] tobe output by the addition-type first-order transversal filter 31 in thetransversal filter 30 of FIG. 1. Therefore, a digital signal X₃[n·T_(s)]to be output by the addition-type first-order transversal filter 32 inthe transversal filter 30 indicates the same value as that in theabove-described Embodiment 1.

Hence, the computation of a phase frequency computer 4 is the same asthat in the above-described Embodiment 1, and thus, the sameadvantageous effects as those in the above-described Embodiment 1 can beobtained.

In addition, since the transversal filter 30 does not require theaddition-type first-order transversal filter 31, the circuitry size canbe reduced over the above-described Embodiment 1.

Embodiment 7

The above-described Embodiment 1 represents that the transversal filter10 is constituted by the subtraction-type first-order transversalfilters 11 and 12, each of which is the first subtraction-typefirst-order transversal filter D shown in FIG. 2A, are connected inseries with each other. On the other hand, Embodiment 7 described belowrepresents a transversal filter 10 constituted by different circuitriesfrom those of the transversal filter 10 shown in FIG. 1.

FIG. 8 is a configuration diagram illustrating a transversal filter 10of a phase frequency detection device of the Embodiment 7 of theinvention.

In FIG. 8, splitter circuitry 91 splits an input digital signal X_(in)into two.

One-sampling time delaying circuitry 92 is first delaying circuitry thatdelays one digital signal split by the splitter circuitry 91 by onesampling time T_(s).

One-sampling time delaying circuitry 93 is second delaying circuitrythat delays, by one sampling time T_(s), the digital signal which hasbeen delayed by the one-sampling time delaying circuitry 92.

Coefficient multiplication circuitry 94 multiplies, by a factor of −2,the digital signal having been delayed by the one-sampling time delayingcircuitry 92.

Addition computation circuitry 95 performs an addition computation amongthe digital signal delayed by the one-sampling time delaying circuitry93, the digital signal multiplied by the factor by the coefficientmultiplication circuitry 94, and the other digital signal split by thesplitter circuitry 91.

Next, operation will be described.

The addition computation circuitry 95 adds together: a digital signaldelayed by two sampling times T_(s) through the one-sampling timedelaying circuitries 92 and 93; a digital signal that has been delayedby one sampling time T_(s) through the one-sampling time delayingcircuitry 92 before being multiplied by a factor of −2 at thecoefficient multiplication circuitry 94; and a digital signal split bythe splitter circuitry 91. A transfer characteristic DF₁ of thetransversal filter 10, which has the constitution shown in FIG. 8, isgiven by the following equation (20).

DF ₁ =Z ⁻²−2·Z ⁻¹+1  (20)

In equation (20), Z⁻¹ is a complex number of exp(−jω·T_(s)) and denotesa delay of one sampling time. Z⁻² represents a delay of two samplingtimes.

On the other hand, the transfer characteristic DF₁ of the transversalfilter 10 shown in FIG. 1 is given by the following equation (21). Thisis based on the constitution where the subtraction-type first-ordertransversal filters 11 and 12 being the first subtraction-typefirst-order transversal filter D shown in FIG. 2A are connected inseries with each other.

DF ₁=(1−Z ⁻¹)(1−Z ⁻¹)=Z ⁻²−2·Z ⁻¹+1  (21)

According to the equations (20) and (21), the transfer characteristicDF₁ of the transversal filter 10 of FIG. 8 is the same as the transfercharacteristic DF₁ of the transversal filter 10 of FIG. 1. Therefore,the transversal filter 10 of FIG. 8 may be utilized in place of thetransversal filter 10 of FIG. 1.

Embodiment 8

The above-described Embodiment 1 represents that the transversal filter20 is constituted such that the subtraction-type first-order transversalfilter 21 being the first subtraction-type first-order transversalfilter D shown in FIG. 2A is connected in series with the addition-typefirst-order transversal filter 22 being the first addition-typefirst-order transversal filter I shown in FIG. 2C. Embodiment 8described below is assumed that a transversal filter 20 is constitutedby different circuitries from those of the transversal filter 20 shownin FIG. 1.

FIG. 9 is a configuration diagram illustrating a transversal filter 20of a phase frequency detection device of the Embodiment 8 of theinvention.

In FIG. 9, splitter circuitry 101 splits an input digital signal X_(in)into two.

One-sampling time delaying circuitry 102 is first delaying circuitrythat delays one digital signal split by the splitter circuitry 101 byone sampling time T_(s).

One-sampling time delaying circuitry 103 is a second delaying circuitrythat delays, by one sampling time T_(s), the digital signal which hasbeen delayed by the one-sampling time delaying circuitry 102.

Coefficient multiplication circuitry 104 multiplies, by a factor of −1,the digital signal having been delayed by the one-sampling time delayingcircuitry 103.

Addition computation circuitry 105 performs an addition computationbetween the digital signal multiplied by the factor by the coefficientmultiplication circuitry 104 and the other digital signal split by thesplitter circuitry 101.

Next, operation will be described.

The addition computation circuitry 105 adds together: a digital signalhaving been delayed by two sampling times T_(s) through the one-samplingtime delaying circuitries 102 and 103 before being multiplied by afactor of −1 by the coefficient multiplication circuitry 104; and adigital signal split by the splitter circuitry 101. The transfercharacteristic DF₂ of the transversal filter 20 having the constitutionshown in FIG. 9 is given by the following equation (22).

DF ₂=1−Z ⁻²  (22)

On the other hand, the transfer characteristic DF₂ of the transversalfilter 20 of FIG. 1 is as shown in the following equation (23). This isbased on the constitution where

the subtraction-type first-order transversal filters 21 which is thefirst subtraction-type first-order transversal filter D shown in FIG. 2Ais connected in series with the addition-type first-order transversalfilter 22 which is the first addition-type first-order transversalfilter I shown in FIG. 2C:

DF ₂=(1−Z ⁻¹)·(1+Z ⁻¹)=1−Z ⁻²  (23)

According to the equations (22) and (23), the transfer characteristicDF₂ of the transversal filter 20 of FIG. 9 is the same as the transfercharacteristic DF₂ of the transversal filter 20 of FIG. 1. Therefore,the transversal filter 20 of FIG. 9 may be utilized in place of thetransversal filter 20 of FIG. 1.

Embodiment 9

The above-described Embodiment 1 represents that the transversal filter30 is constituted by the addition-type first-order transversal filters31 and 32, each of which is the first addition-type first-ordertransversal filter I shown in FIG. 2C, are connected in series with eachother. Embodiment 9 described below represents a transversal filter 30which is constituted by different circuitries from those of thetransversal filter 30 of FIG. 1.

FIG. 10 is a configuration diagram illustrating a transversal filter 30of a phase frequency detection device of the Embodiment 9 of theinvention.

In FIG. 10, splitter circuitry 111 splits an input digital signal X_(in)into two.

One-sampling time delaying circuitry 112 is first delaying circuitrythat delays one digital signal split by the splitter circuitry 111 byone sampling time T_(s).

One-sampling time delaying circuitry 113 is second delaying circuitrythat delays, by one sampling time T_(s), the digital signal having beendelayed by the one-sampling time delaying circuitry 112.

Coefficient multiplication circuitry 114 multiplies, by a factor of 2,the digital signal having been delayed by the one-sampling time delayingcircuitry 112.

Addition computation circuitry 115 is circuitry that performs anaddition computation among the digital signal delayed by theone-sampling time delaying circuitry 113, the digital signal multipliedby the factor by the coefficient multiplication circuitry 114, and theother digital signal split by the splitter circuitry 111.

Next, operation will be described.

The addition computation circuitry 115 adds together: a digital signaldelayed by two sampling times T_(s) through the one-sampling timedelaying circuitries 112 and 113; a digital signal delayed by onesampling time T_(s) by the one-sampling time delaying circuitry 112before being multiplied by a factor of 2 at the coefficientmultiplication circuitry 114; and a digital signal split by the splittercircuitry 111. The transfer characteristic DF₃ of the transversal filter30 shown in FIG. 10 is given by the following equation (24).

DF ₃ =Z ⁻²+2·Z ⁻¹+1  (24)

On the other hand, the transfer characteristic DF₃ of the transversalfilter 30 shown in FIG. 1 is given by the following equation (25). Thisis based on the constitution where the addition-type first-ordertransversal filters 31 and 32, each of which is the first addition-typefirst-order transversal filter I shown in FIG. 2C, are connected inseries with each other.

DF ₃=(Z ⁻¹+1)·(Z ⁻¹+1)=Z ⁻²+2·Z ⁻¹+1  (25)

According to the equations (24) and (25), the transfer characteristicDF₃ of the transversal filter 30 shown in FIG. 10 is the same as thetransfer characteristic DF₃ of the transversal filter 30 of FIG. 1.Therefore, the transversal filter 30 of FIG. 10 may be utilized in placeof the transversal filter 30 of FIG. 1.

Embodiment 10

The above-described Embodiment 1 represents the filter circuitry 1 thatis constituted by the transversal filters 10, 20, and 30. Each of thetransversal filters 10, 20, and 30 may be constituted to include adigital filter for removing noise which has been superimposed on aninput digital signal X_(in).

FIG. 11 is a configuration diagram illustrating filter circuitry 1 of aphase frequency detection device of Embodiment 10 of the invention. InFIG. 11, the same reference signs as those in FIG. 1 indicate the sameor corresponding portions and thus description thereof is omitted.

A digital filter 13 removes noise superimposed on a digital signal whichis output by a subtraction-type first-order transversal filter 12.

A digital filter 23 removes noise superimposed on a digital signal whichis output by an addition-type first-order transversal filter 22.

A digital filter 33 removes noise superimposed on a digital signal whichis output by an addition-type first-order transversal filter 32.

The circuitry configuration of the digital filters 13, 23, and 33 is notparticularly limited as long as the ones are capable of removing noisesuperimposed on a digital signal X_(in). For example, an FIR (FiniteImpulse Response) filter or an IIR (Infinite Impulse Response) filtermay be used as each digital filter.

Note that, in order to detect a phase θ_(X)[n·T_(s)] and a frequencyf_(X)[n·T_(s)] of a digital signal X_(in)[n·T_(s)] by the phasefrequency computer 4 of FIG. 1, the digital filters 13, 23, and 33 arerequired to have the same transfer characteristic DF among them.

FIG. 11 represents an example in which the digital filters 13, 23, and33 are applied to the filter circuitry 1 of FIG. 1. The digital filters13 and 33 may be applied to the filter circuitry 1 constituted by thetwo transversal filters 10 and 30 shown in FIG. 4.

The Embodiment 10 represents that each of the digital filters 13, 23,and 33 of the corresponding transversal filters 10, 20, and 30 isdisposed as an output stage of a series of the two first-ordertransversal filters. Alternatively, as shown in FIG. 12, each of thedigital filters 13, 23, and 33 may be disposed as an input stage of theseries of the two first-order transversal filters to remove noisesuperimposed on an input digital signal.

Further alternatively, as shown in FIG. 13, a digital filter 13 may beconnected as a previous stage to the filter circuitry 1 to remove noisesuperimposed on an input digital signal.

Embodiment 11

FIG. 14 is a configuration diagram illustrating a phase frequencydetection device of Embodiment 11 of the invention. In FIG. 14, the samereference signs as those in FIG. 1 indicate the same or correspondingportions and thus description thereof is omitted.

A phase frequency computer 121 has the same configuration as the phasefrequency computer 4 of FIG. 1. The phase frequency computer 121performs phase computation and frequency computation using digitalsignals X₁, X₂, and X₃ output by transversal filters 10, 20, and 30, andthereby computes a phase θ_(X) and a frequency f_(X) of an input digitalsignal X_(in).

A phase frequency computer 122 has the same configuration as the phasefrequency computer 4 of FIG. 4. The phase frequency computer 122performs phase computation and frequency computation that use thedigital signals X₁ and X₃ output by the transversal filters 10 and 30,and thereby computes a phase θ_(X) and a frequency f_(X) of the inputdigital signal X_(in).

As presented in the above-described Embodiments 1 and 3, the phasefrequency computer 4 of FIG. 1 and the phase frequency computer 4 ofFIG. 4 differ from each other in contents of phase computation andfrequency computation.

A statistics computer 123 performs a statistical computation using thephase θ_(X) computed by the phase frequency computer 121 and the phaseθ_(X) computed by the phase frequency computer 122, and also performs astatistical computation using the frequency f_(X) computed by the phasefrequency computer 121 and the frequency f_(X) computed by the phasefrequency computer 122.

Next, operation will be described.

The phase frequency computer 121 computes a phase θ_(X)[n·T_(s)] and afrequency f_(X)[n·T_(s)] of a digital signal X_(in)[n·T_(s)] in the samemanner as the phase frequency computer 4 of FIG. 1.

The phase frequency computer 122 computes a phase θ_(X)[n·T_(s)] and afrequency f_(X)[n·T_(s)] of the digital signal X_(in)[n·T_(s)] in thesame manner as the phase frequency computer 4 of FIG. 4.

If the number of bits applied to digital computation performed by thephase frequency computers 121 and 122 is infinite, a quantization errordoes not occur in the digital computation. In this case, a phaseθ_(X)[n·T_(s)] obtained by the equation (12) and a phase θ_(X)[n·T_(s)]obtained by the equation (19) have the same value as each other, and afrequency f_(X)[n·T_(s)] obtained by the equation (13) and a frequencyf_(X)[n·T_(s)] obtained by the equation (18) have the same value as eachother.

However, since the number of bits applied to digital computationperformed by the phase frequency computers 121 and 122 has a finitevalue, the quantization error may occur.

Hence, the statistics computer 123 performs a statistical computation onthe phase θ_(X)[n·T_(s)] computed by the phase frequency computer 121and the phase θ_(X)[n·T_(s)] computed by the phase frequency computer122, and also performs a statistical computation on the frequencyf_(X)[n·T_(s)] computed by the phase frequency computer 121 and thefrequency f_(X)[n·T_(s)] computed by the phase frequency computer 122.

Possible statistical computations for the two phases θ_(X)[n·T_(s)]computed by the phase frequency computers 121 and 122 may be acomputation of finding an average value of the two phasesθ_(X)[n·T_(s)], a computation of finding a weighted addition value, etc.

In addition, possible statistical computations for the two frequenciesf_(X)[n·T_(s)] computed by the phase frequency computers 121 and 122 maybe a computation of finding an average value of the two frequenciesf_(X)[n·T_(s)], a computation of finding a weighted addition value, etc.

By those computations, the influence of quantization error occurring indigital computation of the phase frequency computers 121 and 122 can bereduced, enabling to obtain a highly accurate phase θ_(X)[n·T_(s)] andfrequency f_(X)[n·T_(s)].

The Embodiment 11 represents that the phase frequency computers 121 and122 having different processing contents of phase computation andfrequency computation are mounted, and the statistics computer 123performs a statistical computation on the computation results of thephase frequency computers 121 and 122. Alternatively, three or morephase frequency computers having different processing contents of phasecomputation and frequency computation may be mounted, and the statisticscomputer 123 may perform a statistical computation on the computationresults of the three or more phase frequency computers.

The Embodiment 11 represents that the phase frequency computers 121 and122 having different processing contents of phase computation andfrequency computation are mounted. Alternatively, filter circuitries 1connected to previous stages to a plurality of phase frequency computersmay have different configurations, and the statistics computer 123 mayperform a statistical computation on the computation results of theplurality of phase frequency computers.

Specifically, for example as shown in FIG. 15, two phase frequencycomputers 121 may be provided. One of the two phase frequency computers121 computes a phase θ_(X)[n·T_(s)] and a frequency f_(X)[n·T_(s)] of adigital signal X_(in)[n·T_(s)] by using output signals fromcorresponding filter circuitry 1 constituted by transversal filters 10,20, and 30, in which digital filters 13, 23, and 33 are not included.The other one of the two phase frequency computers 121 computes a phaseθ_(X)[n·T_(s)] and a frequency f_(X)[n·T_(s)] of the digital signalX_(in)[n·T_(s)] by using output signals from filter circuitry 1constituted by transversal filters 10, 20, and 30, in which digitalfilters 13, 23, and 33 are included. According to this constitution, astatistics computer 123 performs a statistical computation on the phasesθ_(X)[n·T_(s)] computed by the two phase frequency computers 121 andalso performs a statistical computation on the frequenciesf_(X)[n·T_(s)] computed by the two phase frequency computers 121.

Also in this case, the influence of quantization error occurring indigital computation of the two phase frequency computers 121 is reduced,enabling to obtain a highly accurate phase θ_(X)[n·T_(s)] and frequencyf_(X)[n·T_(s)].

Note that free combinations of the embodiments, or modifications to anycomponent in the embodiments, or omissions of any component in theembodiments which fall within the spirit and scope of the invention maybe made to the invention of the present application.

Phase frequency detection devices according to the invention aresuitable for devices that need to detect a phase θ_(X) and a frequencyf_(X) of an input digital signal X_(in) even if the input digital signalX_(in) is a short-pulse signal.

1: filter circuitry, 4: phase frequency computer, 10: transversal filter(first transversal filter), 11 and 12: subtraction-type first-ordertransversal filter, 13: digital filter, 20: transversal filter (secondtransversal filter), 21: subtraction-type first-order transversalfilter, 22: addition-type first-order transversal filter, 23: digitalfilter, 30: transversal filter (third transversal filter, secondtransversal filter), 31 and 32: addition-type first-order transversalfilter, 33: digital filter, 41: division computation circuitry (firstdivision computation circuitry), 42: division computation circuitry(second division computation circuitry), 43: multiplication computationcircuitry, 44: n-th root computation circuitry (root computationcircuitry), 45: phase computation circuitry, 46: frequency computationcircuitry, 51: splitter circuitry (first splitter circuitry), 52:one-sampling time delaying circuitry (first delaying circuitry), 53 and54: subtraction computation circuitry, 61: splitter circuitry (secondsplitter circuitry), 62: one-sampling time delaying circuitry (seconddelaying circuitry), 63 and 64: addition computation circuitry, 71:multiplication computation circuitry (first multiplication computationcircuitry), 72: multiplication computation circuitry (secondmultiplication computation circuitry), 73: division computationcircuitry, 81: division computation circuitry, 82: n-th root computationcircuitry (root computation circuitry), 83: frequency computationcircuitry, 84: phase computation circuitry, 91: splitter circuitry, 92:one-sampling time delaying circuitry (first delaying circuitry), 93:one-sampling time delaying circuitry (second delaying circuitry), 94:coefficient multiplication circuitry, 95: addition computationcircuitry, 101: splitter circuitry, 102: one-sampling time delayingcircuitry (first delaying circuitry), 103: one-sampling time delayingcircuitry (second delaying circuitry), 104: coefficient multiplicationcircuitry, 105: addition computation circuitry, 111: splitter circuitry,112: one-sampling time delaying circuitry (first delaying circuitry),113: one-sampling time delaying circuitry (second delaying circuitry),114: coefficient multiplication circuitry, 115: addition computationcircuitry, 121 and 122: phase frequency computer, and 123: statisticscomputer

1. (canceled)
 2. A phase frequency detection device comprising: filtercircuitry including a plurality of transversal filters which areconnected in parallel to each other, the plurality of transversalfilters changing amplitude and a phase of an input digital signal andoutputting different digital signals as respective resulting digitalsignals whose amplitude and phase have been changed; and a phasefrequency computer to compute a phase and a frequency of the inputdigital signal by performing phase computation and frequency computationusing the digital signals output by the plurality of transversalfilters, wherein the filter circuitry is constituted such that a firsttransversal filter, a second transversal filter, and a third transversalfilter, as the plurality of transversal filters, are connected inparallel to each other, and the phase frequency computer includes: firstdivision computation circuitry to perform a division computation betweena digital signal output by the first transversal filter and a digitalsignal output by the second transversal filter, and to output a firstdivision computation signal being a result of the division computation;second division computation circuitry to perform a division computationbetween a digital signal output by the third transversal filter and thedigital signal output by the second transversal filter, and to output asecond division computation signal being a result of the divisioncomputation; multiplication computation circuitry to perform amultiplication computation between the first division computation signaloutput by the first division computation circuitry and the seconddivision computation signal output by the second division computationcircuitry, and to output a multiplication computation signal being aresult of the multiplication computation; root computation circuitry toperform a root computation on the multiplication computation signaloutput by the multiplication computation circuitry, and to output a rootcomputation signal being a result of the root computation; phasecomputation circuitry to compute a phase of the input digital signal byusing the root computation signal output by the root computationcircuitry and a sign of the first division computation signal or thesecond division computation signal; and frequency computation circuitryto compute a frequency of the input digital signal by using the phasecomputed by the phase computation circuitry.
 3. A phase frequencydetection device comprising: filter circuitry including a plurality oftransversal filters which are connected in parallel to each other, theplurality of transversal filters changing amplitude and a phase of aninput digital signal and outputting different digital signals asrespective resulting digital signals whose amplitude and phase have beenchanged; and A phase frequency computer to compute a phase and afrequency of the input digital signal by performing phase computationand frequency computation using the digital signals output by theplurality of transversal filters, wherein the filter circuitry isconstituted such that a first transversal filter, a second transversalfilter, and a third transversal filter, as the plurality of transversalfilters, are connected in parallel to each other, and the phasefrequency computer includes: first multiplication computation circuitryto perform a multiplication computation between a digital signal outputby the first transversal filter and a digital signal output by the thirdtransversal filter, and to output a first multiplication computationsignal being a result of the multiplication computation; secondmultiplication computation circuitry to perform a square multiplicationon a digital signal output by the second transversal filter, and tooutput a second multiplication computation signal being a result of thesquare multiplication; division computation circuitry to perform adivision computation between the first multiplication computation signaloutput by the first multiplication computation circuitry and the secondmultiplication computation signal output by the second multiplicationcomputation circuitry, and to output a division computation signal beinga result of the division computation; root computation circuitry toperform a root computation on the division computation signal output bythe division computation circuitry, and to output a root computationsignal being a result of the root computation; phase computationcircuitry to compute a phase of the input digital signal by using theroot computation signal output by the root computation circuitry and asign of the first multiplication computation signal; and frequencycomputation circuitry to compute a frequency of the input digital signalby using the phase computed by the phase computation circuitry.
 4. Aphase frequency detection device comprising: filter circuitry includinga plurality of transversal filters which are connected in parallel toeach other, the plurality of transversal filters changing amplitude anda phase of an input digital signal and outputting different digitalsignals as respective resulting digital signals whose amplitude andphase have been changed; and a phase frequency computer to compute aphase and a frequency of the input digital signal by performing phasecomputation and frequency computation using the digital signals outputby the plurality of transversal filters, wherein the filter circuitry isconstituted such that a first transversal filter and a secondtransversal filter, as the plurality of transversal filters, areconnected in parallel to each other, and the phase frequency computerincludes: division computation circuitry to perform a divisioncomputation between a digital signal output by the first transversalfilter and a digital signal output by the second transversal filter, andto output a division computation signal being a result of the divisioncomputation; root computation circuitry to perform a root computation onthe division computation signal output by the division computationcircuitry, and to output a root computation signal being a result of theroot computation; frequency computation circuitry to compute a frequencyof the input digital signal by using the root computation signal outputby the root computation circuitry; and phase computation circuitry forcomputing a phase of the input digital signal by using the frequencycomputed by the frequency computation circuitry.
 5. A phase frequencydetection device comprising: filter circuitry including a plurality oftransversal filters which are connected in parallel to each other, theplurality of transversal filters changing amplitude and a phase of aninput digital signal and outputting different digital signals asrespective resulting digital signals whose amplitude and phase have beenchanged; and a phase frequency computer to compute a phase and afrequency of the input digital signal by performing phase computationand frequency computation using the digital signals output by theplurality of transversal filters, wherein each of the plurality oftransversal filters is constituted by one or more subtraction-typefirst-order transversal filters connected in series with each other orone or more addition-type first-order transversal filters connected inseries with each other or a subtraction-type first-order transversalfilter and an addition-type first-order transversal filter, which areconnected in series with each other, each of the subtraction-typefirst-order transversal filters is constituted by: first splittercircuitry to split an input digital signal; first delaying circuitry todelay one digital signal split by the first splitter circuitry by onesampling time; and subtraction computation circuitry to perform asubtraction computation between the digital signal delayed by the firstdelaying circuitry and the other digital signal split by the firstsplitter circuitry, and each of the addition-type first-ordertransversal filters is constituted by: second splitter circuitry tosplit an input digital signal; second delaying circuitry to delay onedigital signal split by the second splitter circuitry (61) by onesampling time; and addition computation circuitry to perform an additioncomputation between the digital signal delayed by the second delayingcircuitry and the other digital signal split by the second splittercircuitry.
 6. The phase frequency detection device according to claim 5,wherein the filter circuitry is constituted such that a firsttransversal filter, a second transversal filter, and a third transversalfilter, as the plurality of transversal filters, are connected inparallel to each other, the first transversal filter is constituted bytwo subtraction-type first-order transversal filters which are connectedin series with each other, the second transversal filter is constitutedby the subtraction-type first-order transversal filter and theaddition-type first-order transversal filter, which are connected inseries with each other, and the third transversal filter is constitutedby two addition-type first-order transversal filters which are connectedin series with each other.
 7. The phase frequency detection deviceaccording to claim 5, wherein the filter circuitry is constituted suchthat a first transversal filter and a second transversal filter, as theplurality of transversal filters, are connected in parallel to eachother, and the first transversal filter is constituted by twosubtraction-type first-order transversal filters which are connected inseries with each other, and the second transversal filter is constitutedby two addition-type first-order transversal filters which are connectedin series with each other.
 8. The phase frequency detection deviceaccording to claim 5, wherein the filter circuitry is constituted suchthat a first transversal filter, a second transversal filter, and athird transversal filter, as the plurality of transversal filters, areconnected in parallel to each other, the first transversal filter isconstituted by two subtraction-type first-order transversal filterswhich are connected in series with each other, the second transversalfilter is constituted by an addition-type first-order transversal filterto which is input a digital signal output by a preceding one in the twosubtraction-type first-order transversal filters of the firsttransversal filter, and the third transversal filter is constituted bytwo addition-type first-order transversal filters which are connected inseries with each other.
 9. The phase frequency detection deviceaccording to claim 5, wherein the filter circuitry is constituted suchthat a first transversal filter, a second transversal filter, and athird transversal filter, as the plurality of transversal filters, areconnected in parallel to each other, the first transversal filter isconstituted by two subtraction-type first-order transversal filterswhich are connected in series with each other, the third transversalfilter is constituted by two addition-type first-order transversalfilters which are connected in series with each other, and the secondtransversal filter is constituted by a subtraction-type first-ordertransversal filter to which is input a digital signal output by apreceding one in the two addition-type first-order transversal filtersof the third transversal filter.
 10. The phase frequency detectiondevice according to claim 5, wherein the filter circuitry is constitutedsuch that a first transversal filter, a second transversal filter, and athird transversal filter, as the plurality of transversal filters, areconnected in parallel to each other, the first transversal filter isconstituted by two subtraction-type first-order transversal filterswhich are connected in series with each other, the second transversalfilter is constituted by an input-side addition-type first-ordertransversal filter and an output-side subtraction-type first-ordertransversal filter, which are connected in series with each other; andthe third transversal filter is constituted by an addition-typefirst-order transversal filter to which is input a digital signal outputby the input-side addition-type first-order transversal filter of thesecond transversal filter. 11.-17. (canceled)